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ST8024S com/seg lcd driver datasheet note: sitronix technology corp. reserves the right to change the contents in this document without prior notice. this is not a final specification. some parameters are subject to change. version 0.39 2008/05/05
ST8024S ver 0.39 page 2/27 2008/05/05 1. features n number of lcd drive outputs: 240 n supply voltage for lcd drive: +15.0 to +30.0 v n supply voltage for the logic system: +2.5 to +5.5 v n low power consumption n low output impedance (segment mode) n shift clock frequency ? 20mhz(max.):v dd = +5.0 0.5 v ? 15mhz(max.):v dd = +3.0 to + 4.5 v ? 12mhz(max.):v dd = +2.5 to + 3.0 v n adopts a data bus system n 4-bit/8-bit parallel input modes are selectable with a mode (md) pin n automatic transfer function of an enable signal n automatic counting function which, in the chip selection mode, causes the internal clock to be stopped by automatically counting 240 bits of input data n line latch circuits are reset when /dispoff active (common mode) n shift clock frequency: 4 mhz (max.) n built-in 240-bit bi-directional shift register (divisible into 120 bits x 2) n available in a single mode (240-bit shift register) or in a dual mode (120-bit shift register x 2) ? y 1 ->y 240 single mode ? y 240 ->y 1 single mode ? y 1 ->y l20 , y 121 ->y 240 dual mode ? y 240 ->y 121 , y l20 ->y 1 dual mode the above 4 shift directions are in-selectable n shift register circuits are reset when /dispoff active 2. description the ST8024S is a 240-output segment/common driver ic suitable for driving large/medium scale dot matrix lcd panels, and is used in personal computers/work stations. the ST8024S is good both as a segment driver and a common driver, and it can create a low power consuming, high-resolution lcd.
ST8024S ver 0.39 page 3/27 2008/05/05 3. block diagram 4. functional operations of each block block function active control in case of segment mode, controls the selection or non-selection of the chip. following an lp signal input, and after the chip selection signal is input, a selection signal is generated internally until 240 bits of data have been read in. once data input has been completed, a selection signal for cascade connection is output, and the chip is non-selected. in case of common mode, controls the input/output data of bi-directional pins. sp conversion & data control in case of segment mode, keeps input data which are 2 clocks of xck at 4-bit parallel input mode in latch circuit, or keeps input data which are 1 clock of xck at 8-bit parallel input mode in latch circuit; after that they are put on the internal data bus 8 bits at a time. data latch control in case of segment mode, selects the state of the data latch which reads in the data bus signals. the shift direction is controlled by the control logic. for every 16 bits of data read in, the selection signal shifts one bit based on the state of the control circuit. data latch in case of segment mode, latches the data on the data bus. the latch state of each lcd drive output pin is controlled by the control logic and the data latch control; 240 bits of data are read in 30 sets of 8 bits. line latch/ shift register in case of segment mode, all 240 bits which have been read into the data latch are simultaneously latched at the falling edge of the lp signal, and are output to the level shifter block. in case of common mode, shifts data from the data input pin at the falling edge of the lp signal. level shifter the logic voltage signal is level-shifted to the lcd drive voltage level, and is output to the driver block. 4-level driver drives the lcd drive output pins from the line latch/shift register data, and selects one of 4 levels (v 0 , v 12 , v 43 or vss) based on the s/c, fr and /dispoff signals. control logic controls the operation of each block. in case of segment mode, when an lp signal has been input, all blocks are reset and the control logic waits for the selection signal output from the active control block. once the selection signal has been output, operation of the data latch and data transmission is controlled, 240 bits of data are read in, and the chip is non-selected. in case of common mode, controls the direction of data shift. 240-bit 4-level driver 240-bit level shifter 240-bit line latch/shift register data control sp conversion & data control (4 to 8 or 8 to 8) control logic active control level shifter 8 bit data latch di 0 di 1 di 2 di 3 di 4 di 5 di 6 di 7 v dd v ss v ss v 43l v 12l v 0l y 240 y 239 y 2 y 1 v ss v 43r v 12r v 0r fr /dispoff eio 1 eio 2 lp xck l/r md s/c 8 1616 16 240 240
ST8024S ver 0.39 page 4/27 2008/05/05 5. input/output circuits i v dd to internal circuit gnd (0v) applicable pins l/r , s/c , di 6 ~di 0 , /dispoff , lp , fr , md figure 1 input circuit (1) i v dd to internal circuit applicable pins di 7 , xck gnd (0v) gnd (0v) control signal figure 2 input circuit (2)
ST8024S ver 0.39 page 5/27 2008/05/05 v dd i/o to internal circuit gnd (0v) gnd (0v) control signal gnd (0v) v dd output signal control signal application pins eio 1 , eio 2 figure 3 input/output circuit o gnd (0v) v 0 control signal 1 control signal 3 control signal 2 control signal 4 v 0 v 12 v 43 v ss gnd (0v) application pins y 1 ~y 160 figure 4 lcd drive output circuit
ST8024S ver 0.39 page 6/27 2008/05/05 6. functional description 6.1 pin functions (segment mode) symbol function v dd logic system power supply pin, ? connected to +2.5 to +5.5 v. gnd ground pin lgnd logic ground pin ? do not short lgnd with gnd and vss by ito on lcd panel ? connect it to gnd on pcb or fpc. v ss connect to gnd by ito on lcd panel. v 0l , v 0r v 12l , v 12r v 43l , v 43r bias power supply pins for lcd drive voltage ? normally use the bias voltages set by a resistor divider ? ensure that voltages are set such that v ss < v 43 < v 12 < v 0 . ? v il and v ir (i = 0,12, 43) must connect to an external power supply, and supply regular voltage which is assigned by specification for each power pin di 7 -di 0 input pins for display data ? in 4-bit parallel mode, di 3 -di 0 are the display data input pins, and di 7 -di 4 must be connected to lgnd or v dd . ? in 8-bit parallel mode, all di 7 -dl 0 pins are the display data input pins. ? refer to section 6.2.2. xck clock input pin for taking display data ? data is read at the falling edge of the clock pulse. lp latch pulse input pin for display data ? data is latched at the falling edge of the clock pulse. l/r input pin for selecting the reading direction of display data ? when set to lgnd level "l", data is read sequentially from y 240 to y 1 . ? when set to v dd level "h", data is read sequentially from y 1 to y 240 . refer to section 6.2.2. /dispoff control input pin for output of non-select level ? the input signal is level-shifted from logic voltage level to lcd drive voltage level, and controls the lcd drive circuit. ? when set to lgnd level "l", the lcd drive output pins (y 1 -y 240 ) are set to level vss. ? when set to "l", the contents of the line latch are reset, but the display data are read in the data latch regardless of the condition of /dispoff. when the /dispoff function is canceled, the driver outputs non-select level (v 12 or v 43 ), then outputs the contents of the data latch at the next falling edge of the lp. at that time, if /dispoff removal time does not correspond to what is shown in ac characteristics, it can not output the reading data correctly. ? table of truth values is shown in "truth table" in functional operations. fr ac signal input pin for lcd drive waveform ? the input signal is level-shifted from logic voltage level to lcd drive voltage level, and controls the lcd drive circuit. ? normally it inputs a frame inversion signal. ? the lcd drive output pins' output voltage levels can be set using the line latch output signal and the fr signal. ? table of truth values is shown in "truth table" in functional operations. md mode selection pin ? when set to lgnd level "l", 8-bit parallel input mode is set. ? when set to v dd level "h", 4-bit parallel input mode is set. ? refer to section 6.2.2. s/c segment mode/common mode selection pin ? when set to v dd level "h", segment mode is set. elo 1 , eio 2 input/output pins for chip selection ? when l/r input is at lgnd level "l", elo 1 is set for output, and eio 2 is set for input. ? when l/r input is at v dd level "h", elo 1 is set for input, and eio 2 is set for output. ? during output, set to "h" while lp ? xck is "h" and after 240 bits of data have been
ST8024S ver 0.39 page 7/27 2008/05/05 read, set to "l for one cycle (from falling edge to failing edge of xck), after which it returns to "h". ? during input, the chip is selected while el is set to "l" after the lp signal is input. the chip is non-selected after 240 bits of data have been read. y 1 -y 240 lcd drive output pins ? corresponding directly to each bit of the data latch, one level (v 0 , v 12 , v 43 , or v ss ) is selected and output. ? table of truth values is shown in "truth table" in functional operations. (common mode) symbol function v dd logic system power supply pin, connected to +2.5 to +5.5 v. gnd ground pin lgnd logic ground pin ? do not short lgnd with gnd and vss by ito on lcd panel ? connect it to gnd on pcb or fpc. v ss connect to gnd by ito on lcd panel. v 0l , v 0r v 12l , v 12r v 43l , v 43r bias power supply pins for lcd drive voltage ? normally use the bias voltages set by a resistor divider. ? ensure that voltages are set such that v ss < v 43 < v 12 < v 0 . ? v il and v ir (i = 0,12, 43) must connect to an external power supply, and supply regular voltage which is assigned by specification for each power pin. elo 1 shift data input/output pin for bi-directional shift register ? output pin when l/r is at lgnd level "l', input pin when l/r is at v dd level "h". ? when l/r = h, elo 1 is used as input pin, it will be pulled down. ? when l/r = l, elo 1 is used as output pin, it won't be pulled down. ? refer to section 6.2.2. eio 2 shift data input/output pin for bi-directional shift register ? input pin when l/r is at lgnd level "l", output pin when l/r is at v dd level "h". ? when l/r = l, eio 2 is used as input pin, it will be pulled down. ? when l/r = h, eio 2 is used as output pin, it won't be pulled down. ? refer to section 6.2.2. lp shift clock pulse input pin for bi-directional shift register ? data is shifted at the falling edge of the clock pulse. l/r input pin for selecting the shift direction of bi-directional shift register ? data is shifted from y 240 to y 1 when set to lgnd level "l", and data is shifted from y 1 to y 240 when set to v dd level "h". ? refer to section 6.2.2. /dispoff control input pin for output of non-select level ? the input signal is level-shifted from logic voltage level to lcd drive voltage level, and controls the lcd drive circuit. ? when set to lgnd level "l", the lcd drive output pins (y 1 -y 240 ) are set to level lgnd. ? when set to "l , the contents of the shift register are reset to not reading data. when the /dispoff function is canceled, the driver outputs non-select level (v 12 or v 43 ), and the shift data is read at the next falling edge of the lp. at that time, if /dispoff removal time does not correspond to what is shown in ac characteristics, the shift data is not read correctly. ? table of truth values is shown in "truth table" in functional operations. fr ac signal input pin for lcd drive waveform ? the input signal is level-shifted from logic voltage level to lcd drive voltage level, and controls the lcd drive circuit. ? normally it inputs a frame inversion signal. ? the lcd drive output pins' output voltage levels can be set using the shift register output signal and the fr signal. ? table of truth values is shown in "truth table" in functional operations. md mode selection pin ? when set to lgnd level "l", single mode operation is selected; when set to v dd level
ST8024S ver 0.39 page 8/27 2008/05/05 "h" dual mode operation is selected. ? refer to section 6.2.2. di 7 dual mode data input pin ? according to the data shift direction of the data shift register, data can be input starting from the 121st bit. when the chip is used in dual mode, di 7 will be pulled down. when the chip is used in single mode, di 7 won't be pulled down. ? refer to section 6.2.2. s/c segment mode/common mode selection pin ? when set to lgnd level "l", common mode is set. di 6 -di 0 not used ? connect di 6 -di 0 to lgnd or v dd , avoiding floating. xck not used ? xck is pulled down in common mode, so connect to lgnd or open. y 1 -y 240 lcd drive output pins ? corresponding directly to each bit of the shift register, one level (v 0 , v 12 , v 43 , or v ss ) is selected and output. ? table of truth values is shown in "truth table" in functional operations. 6.2 functional operations 6.2.1 truth table (segment mode) fr latch data /dispoff lcd drive output voltage level (y1-y240) l l h v 43 l h h v ss h l h v 12 h h h v 0 x x l v ss (common mode) fr latch data /dispoff lcd drive output voltage level (y1-y240) l l h v 43 l h h v 0 h l h v 12 h h h v ss x x l v ss notes: 1. v ss < v 43 < v 12 < v 0 2. l: lgnd (0 v), h: v dd (+2.5 to +5.5 v), x: don't care 3. "don't care" should be fixed to "h" or "l", avoiding floating. there are two kinds of power supply (logic level voltage and lcd drive voltage) for the lcd driver. supply regular voltage which is assigned by specification for each power pin.
ST8024S ver 0.39 page 9/27 2008/05/05 6.2.2 relationship between the display data and lcd drive output pins (segment mode) (a) 4-bit parallel input mode number of clocks md l/r eio 1 ei0 2 data input 60 clock 59 clock 58 clock di 0 y 1 y 5 y 9 y 229 y 233 y 237 dl 1 y 2 y 6 y 10 y 230 y 234 y 238 di 2 y 3 y 7 y 11 y 231 y 235 y 239 h l output input di 3 y 4 y 8 y 12 y 232 y 236 y 240 di 0 y 240 y 236 y 232 y 12 y 8 y 4 dl 1 y 239 y 235 y 231 y 11 y 7 y 3 di 2 y 238 y 234 y 230 y 10 y 6 y 2 h h input output di 3 y 237 y 233 y 229 y 9 y 5 y 1 (b) 8-bit parallel input mode number of clocks md l/r eio 1 ei0 2 data input 30 clock 29 clock 28 clock di 0 y 1 y 9 y 17 y 217 y 225 y 233 dl 1 y 2 y 10 y 18 y 218 y 226 y 234 di 2 y 3 y 11 y 19 y 219 y 227 y 235 di 3 y 4 y 12 y 20 y 220 y 228 y 236 di 4 y 5 y 13 y 21 y 221 y 229 y 237 di 5 y 6 y 14 y 22 y 222 y 230 y 238 di 6 y 7 y 15 y 23 y 223 y 231 y 239 l l output input di 7 y 8 y 16 y 24 y 224 y 232 y 240 di 0 y 240 y 232 y 224 y 24 y 16 y 8 dl 1 y 239 y 231 y 223 y 23 y 15 y 7 di 2 y 238 y 230 y 222 y 22 y 14 y 6 di 3 y 237 y 229 y 221 y 21 y 13 y 5 di 4 y 236 y 228 y 220 y 20 y 12 y 4 dl 5 y 235 y 227 y 219 y 19 y 11 y 3 di 6 y 234 y 226 y 218 y 18 y 10 y 2 l h input output di 7 y 233 y 225 y 217 y 17 y 9 y 1 (common mode) md l/r data transfer direction eio 1 ei0 2 di 7 l y 240 y 1 output input x l (single) h y 1 y 240 input output x y 240 y 121 l y 120 y 1 output input input y 1 y 120 h (dual) h y 121 y 240 input output input notes: 1. l: lgnd (0 v), h: v dd (+2.5 to +5.5 v), x: don't care 2. "don't care" should be fixed to "h" or "l", avoiding floating.
ST8024S ver 0.39 page 10/27 2008/05/05 6.2.3 connection examples of plural segment drivers (a) when l/r = l y 240 y 240 y 240 y 1 y 1 y 1 eio2eio2eio2eio1eio1eio1 xck lp md fr di 7 -di 0 x c k l p m d f r d i 7 - d i 0 x c k l p m d f r d i 7 - d i 0 x c k l p m d f r d i 7 - d i 0 l/rl/rl/r lgnd 8 top datalast data data flow (b) when l/r = h y 240 y 240 y 240 y 1 y 1 y 1 eio2eio2eio2eio1eio1eio1 xck lp md fr di 7 -di 0 x c k l p m d f r d i 7 - d i 0 l/rl/rl/r v dd 8 top data last data x c k l p m d f r d i 7 - d i 0 x c k l p m d f r d i 7 - d i 0 lgnd data flow
ST8024S ver 0.39 page 11/27 2008/05/05 6.2.4 timing chart of 4-device cascade connection of segment drivers n*n*n*n*n*1111122222 device adevice bdevice cdevice d top datalast data *n = 60 in 4-bit parallel input mode *n = 30 in 8-bit parallel input mode eo (device c) eo (device b) eo (device a) ei (device a) di 7 - di 0 xck lp fr
ST8024S ver 0.39 page 12/27 2008/05/05 6.2.5 connection examples for plural common drivers (a) single mode (l/r = l ) y 240 y 240 y 240 y 1 y 1 y 1 eio2eio2eio2eio1eio1eio1 lp lgnd fr /dispoff l / r l p m d f r lgnd(v dd ) first last flm / d i s p o f f l / r l p m d f r d i 7 / d i s p o f f l / r l p m d f r d i 7 / d i s p o f f d i 7 data flow (b) single mode (l/r = h ) y 240 y 240 y 240 y 1 y 1 y 1 eio2eio2eio2eio1eio1eio1 fr l / r / d i s p o f f m d f r d i 7 lp /dispoff lgnd (v dd ) first last l p lgnd v dd flm l / r / d i s p o f f m d f r d i 7 l p l / r / d i s p o f f m d f r d i 7 l p data flow
ST8024S ver 0.39 page 13/27 2008/05/05 (c) dual mode (l/r = l ) y 240 y 240 y 240 y 1 y 1 y 1 eio2eio2eio2eio1eio1eio1 lp lgnd fr /dispoff l / r l p m d f r d i 7 lgnd(v dd ) first last 2 flm1 / d i s p o f f l / r l p m d f r d i 7 / d i s p o f f l / r l p m d f r d i 7 / d i s p o f f first 2last 1 y 121 y 120 flm2 v dd data flow (d) dual mode (l/r = h ) y 240 y 240 y 240 y 1 y 1 y 1 eio2eio2eio2eio1eio1eio1 fr l / r / d i s p o f f m d f r d i 7 lp /dispoff lgnd (v dd ) first 1 last 2 l p lgnd v dd flm1 l / r / d i s p o f f m d f r d i 7 l p l / r / d i s p o f f m d f r d i 7 l p last 1first 2 y 120 y 121 flm2 data flow
ST8024S ver 0.39 page 14/27 2008/05/05 7. precautions precautions when connecting or disconnecting the power supply this ic has a high-voltage lcd driver, so it may be permanently damaged by a high current which may flow if voltage is supplied to the lcd drive power supply while the logic system power supply is floating. the details are as follows, ? when connecting the power supply, connect the lcd drive power after connecting the logic system power. furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the lcd drive power ? it is advisable to connect the serial resistor (50 to 100 ) or fuse to the lcd drive power v 0 of the system as a current limiter. set up a suitable value of the resistor in consideration of the display grade. and when connecting the logic power supply, the logic condition of this ic inside is insecure. therefore connect the lcd drive power supply after resetting logic condition of this ic inside on /dispoff function. after that, cancel the /dispoff function after the lcd drive power supply has become stable. furthermore, when disconnecting the power, set the lcd drive output pins to level lgnd on /dispoff function. then disconnect the logic system power after disconnecting the lcd drive power. when connecting the power supply, follow the recommended sequence shown here . v dd lgnd v dd lgnd v 0 gnd v dd /dispoff v 0
ST8024S ver 0.39 page 15/27 2008/05/05 8. absolute maximum ratings parameter symbol applicable pins rating unit note supply voltage (1) v dd v dd -0.3 to +7.0 v v 0 v 0l , v 0r -0.3 to +33.0 v v 12 v 12l , v 12r -0.3 to v 0 + 0.3 v v 43 v 43l , v 43r -0.3 to v 0 + 0.3 v supply voltage (2) v ss v ss -0.3 tov 0 +0.3 v input voltage v i di 7 -di 0 , xck, lp, l/r, fr, md, s/c, eio 1 , eio 2 , /dispoff -0.3 to v dd + 0.3 v 1,2 storage temperature t stg -45 to +125 c notes: 1. ta = +25 c 2. the applicable voltage on logic pins with respect to lgnd, high voltage pins with v ss (0 v). 3. stress over the absolute max. ratings conditions will damage the device permanently. 9. recommended operating conditions parameter symbol applicable pins min. typ. max. unit note supply voltage (1) v dd v dd +2.5 +5.5 v supply voltage (2) v 0 v 0l , v 0r +15.0 +30.0 v 1, 2 operating temperature t opr -25 +85 c notes: 1. the applicable voltage on logic pins with respect to lgnd, high voltage pins with v ss (0 v). 2. ensure that voltages are set such that v ss < v 43 < v l2 < v 0 .
ST8024S ver 0.39 page 16/27 2008/05/05 10. electrical characteristics 10.1 dc characteristics (segment mode) (lgnd=v ss = gnd = 0v, v dd = +2.5 to +5.5v, v 0 = +15.0 to +30.0v, t opr = -25 to +85 c) parameter symbol conditions applicable pins min. typ. max. unit note input "low" voltage v il 0.2v dd v input "high" voltage v ih di 7 -di 0 , xck, lp, l/r fr, md, s/c, eio 1 , eio 2 , /dispoff 0.8v dd v dd +0.8 v output "low" voltage v ol i ol = +0.4 ma +0.4 v output "high" voltage v oh i oh = -0.4 ma eio 1 , eio 2 v dd -0.4 v i lil v i = lgnd -10.0 a input leakage current i lih v i = v dd di 7 -di 0 , xck, lp, l/ r fr, md, s/c, eio 1 , eio 2 , /dispoff + 10.0 a v 0 =30v 1.5 2.0 output resistance r on | ? v on | =0.5v v 0 =20v y 1 -y 240 2.0 2.5 k standby current i stb lgnd 75.0 a 1 supply current (1) (non-selection) i dd1 v dd 2.0 ma 2 supply current (2) (selection) i dd2 v dd 12.0 ma 3 supply current (3) i 0 v 0l , v 0r 1.5 ma 4 notes: 1. v dd = +5.0 v, v 0 = +30.0 v, vi = lgnd. 2. v dd = +5.0 v, v 0 = +30.0 v, f xck = 20 mhz, no-load, el = v dd . the input data is turned over by data taking clock (4-bit parallel input mode). 3. v dd = +5.0 v, v 0 = +30.0 v, f xck = 20 mhz, no-load, el = lgnd. the input data is turned over by data taking clock (4-bit parallel input mode). 4. v dd = +5.0 v, v 0 = +30.0 v, f xck = 20mhz, f lp = 41.6 khz, f fr = 80 hz, no-load. the input data is turned over by data taking clock (4-bit parallel input mode). (common mode) (lgnd=v ss = gnd = 0v, v dd = +2.5 to +5.5v, v 0 = +15.0 to +30.0v, t opr = -25 to +85 c) parameter symbol conditions applicable pins min. typ. max. unit note input "low" voltage v il 0.2v dd v input "high" voltage v ih di 7 -di 0 , xck, lp, l/ r fr, md, s/c, eio 1 , eio 2 , /dispoff 0.8v dd v dd +0.8 v output "low" voltage v ol i ol = +0.4 ma +0.4 v output "high" voltage v oh i oh = -0.4 ma eio 1 , eio 2 v dd -0.4 v i lil v i = lgnd di 7 -di 0 , xck, lp, l/ r fr, md, s/c, eio 1 , eio 2 , /dispoff -10.0 a input leakage current i lih v i = v dd di 6 -di 0 , lp, l/r, fr, md, s/c, /dispoff +10.0 a input pull-down current i pd v i = v dd di 7 , xck, eio 1 , eio 2 100.0 a v 0 =30v 1.5 2.0 output resistance r on | ? v on | =0.5v v 0 =20v y 1 -y 240 2.0 2.5 k standby current i spd lgnd 75.0 a 1 supply current (1) i dd v dd 120.0 a 2 supply current (2) i 0 v 0l , v 0r 240.0 a 2 notes: 1. v dd = +5.0 v, v 0 = +30.0 v, v i = lgnd 2. v dd = +5.0 v, v 0 = +30.0 v, f lp = 41.6 khz, f fr = 80 hz, 1/480 duty operation, no-load.
ST8024S ver 0.39 page 17/27 2008/05/05 10.2 ac characteristics (segment mode 1) (lgnd=v ss = gnd = 0v, v dd = +5.0 0.5v, v 0 = +15.0 to +30.0v, t opr = -25 to +85 c) parameter symbol conditions min typ. max. unit note shift clock period t wck t r ,t f 10ns 50 ns 1 shift clock "h" pulse width t wckh 15 ns shift clock "l" pulse width t wckl 15 ns data setup time t ds 10 ns data hold time t dh 12 ns latch pulse "h" pulse width t wlph 15 ns shift clock rise to latch pulse rise time t ld 0 ns shift clock fall to latch pulse fall time t sl 30 ns latch pulse rise to shift clock rise time t ls 25 ns latch pulse fall to shift clock fall time t lh 25 ns enable setup time t s 10 ns input signal rise time t r 50 ns 2 input signal fall time t f 50 ns 2 /dispoff removal time t sd 100 ns /dispoff "l" pulse width t wdl 1.2 s output delay time (1) t d cl = 15 pf 30 ns output delay time (2) t pd1 , t pd2 cl = 15 pf 1.2 s output delay time (3) t pd3 cl = 15 pf 1.2 s notes: 1. takes the cascade connection into consideration. 2. (t wck - t wckh - t wckl )/2 is maximum in the case of high speed operation. (segment mode 2) (lgnd=v ss = gnd = 0v, v dd = +3.0 to +4.5v, v 0 = +15.0 to +30.0v, t opr = -25 to +85 c) parameter symbol conditions min. typ. max. unit note shift clock period t wck t r ,t f 10ns 66 ns 1 shift clock "h" pulse width t wckh 23 ns shift clock "l pulse width t wckl 23 ns data setup time t ds 15 ns data hold time t dh 23 ns latch pulse "h" pulse width t wlph 30 ns shift clock rise to latch pulse rise time t ld 0 ns shift clock fall to latch pulse fall time t sl 50 ns latch pulse rise to shift clock rise time t ls 30 ns latch pulse fall to shift clock fall time t lh 30 ns enable setup time t s 15 ns input signal rise time t r 50 ns 2 input signal fall time t f 50 ns 2 /dispoff removal time t sd 100 ns /dispoff "l" pulse width t wdl 1.2 s output delay time (1) t d cl = 15 pf 41 ns output delay time (2) t pd1 , t pd2 cl = 15 pf 1.2 s output delay time (3) t pd3 cl = 15 pf 1.2 s notes: 1. takes the cascade connection into consideration. 2. (t wck - t wckh - t wckl )/2 is maximum in the case of high speed operation.
ST8024S ver 0.39 page 18/27 2008/05/05 (segment mode 3) (lgnd=v ss = gnd = 0v, v dd = +2.5 to +3.0v, v 0 = +15.0 to +30.0v, t opr = -25 to +85 c) parameter symbol conditions min. typ. max. unit note shift clock period t wck t r ,t f 10ns 82 ns 1 shift clock "h" pulse width t wckh 28 ns shift clock "l pulse width t wckl 28 ns data setup time t ds 20 ns data hold time t dh 23 ns latch pulse "h" pulse width t wlph 30 ns shift clock rise to latch pulse rise time t ld 0 ns shift clock fall to latch pulse fall time t sl 65 ns latch pulse rise to shift clock rise time t ls 30 ns latch pulse fall to shift clock fall time t lh 30 ns enable setup time t s 15 ns input signal rise time t r 50 ns 2 input signal fall time t f 50 ns 2 /dispoff removal time t sd 100 ns /dispoff "l" pulse width t wdl 1.2 s output delay time (1) t d cl = 15 pf 57 ns output delay time (2) t pd1 , t pd2 cl = 15 pf 1.2 s output delay time (3) t pd3 cl = 15 pf 1.2 s notes: 1. takes the cascade connection into consideration. 2. (t wck - t wckh - t wckl )/2 is maximum in the case of high speed operation. (common mode) (lgnd=v ss = 0v, v dd = +2.5 to +5.5v, v 0 = +15.0 to +30.0v, t opr = -25 to +85 c) parameter symbol conditions min. typ. max. unit shift clock period t wlp t r ,t f 20ns 250 ns v dd = +5.0 0.5v 15 ns shift clock "h" pulse width t wlph v dd = +2.5+ 4.5v 30 ns data setup time t su 30 ns data hold time t h 50 ns input signal rise time t r 50 ns input signal fall time t f 50 ns /dispoff removal time t sd 100 ns /dispoff "l" pulse width t wdl 1.2 s output delay time (1) t dl cl = 15 pf 200 ns output delay time (2) t pd1 , t pd2 cl = 15 pf 1.2 s output delay time (3) t pd3 cl = 15 pf 1.2 s
ST8024S ver 0.39 page 19/27 2008/05/05 10.3 timing chart of segment mode lp xck di 7 - di 0 /dispoff t wlph t ld t sl t lh t ls t wckh t f t r t wck t ds t dh top datalast data t wdl t sd t wckl t s 12 n* t d lp xck ei eo *n = 60 in 4-bit parallel input mode *n = 30 in 8-bit parallel input mode fr lp /dispoff y 1 - y 240 t pd1 t pd3 t pd2 fig. 8 timing characteristics (3)
ST8024S ver 0.39 page 20/27 2008/05/05 10.4 timing chart of common mode lp eio 2 eio 1 /dispoff t wdl t sd t dl t h t su t wlp t r t wlph t f fr lp /dispoff y 1 - y 240 t pd1 t pd3 t pd2
ST8024S ver 0.39 page 21/27 2008/05/05 11. application circuit 11.1 application circuit for module f r l p / d i s p o f f x c k e i o 2 s / c l / r e i o 1 c o n t r o l l e r m d d i 0 ~ d i 7 11.2 lcd panel layout example pin name ito resistor values lgnd, gnd, v dd , vss less than 75 when v dd R 3.0v, and the smaller the better v0r, v0l less than 150 , and the smaller the better v12r, v12l, v34r, v12l less than 250 , and the smaller the better ps : above resistor value test on 3 lcd panel.
ST8024S ver 0.39 page 22/27 2008/05/05 12. pad diagram notes: subtract should be connected to gnd. unit : um pad# name x y pad# name x y 1 v 0l - 4180.00 264.00 38 v ss 4192.50 - 355.00 2 v 0l - 4180.00 214.50 39 v ss 4180.00 16.50 3 v 12l - 4180.00 148.50 40 v 34r 4180.00 82.50 4 v 34l - 4180.00 82.50 41 v 12r 4180.00 148.50 5 v ss - 4180.00 16.50 42 v 0r 4180.00 214.50 6 v ss - 4192.50 - 355.00 43 v 0r 4180.00 264.00 7 gnd - 3995.95 - 383.10 44 v 0r 4192.50 350.00 8 gnd - 3815.75 - 383.10 45 dummy 4123.70 350.00 9 lgnd - 3714.45 - 383.10 46 dummy 4090.70 350.00 10 v dd - 3611.80 - 383.35 47 dummy 4057.70 350.00 11 v dd - 3426.65 - 379.35 48 dummy 402 4.70 350.00 12 s/c - 3178.35 - 383.10 49 y 1 3991.70 350.00 13 eio 2 - 2930.15 - 383.10 50 y 2 3958.70 350.00 14 dummy - 2657.85 - 383.10 51 y 3 3925.70 350.00 15 di 0 - 2249.05 - 383.10 52 y 4 3892.70 350.00 16 di 1 - 2009.05 - 383.10 53 y 5 3859.7 0 350.00 17 di 2 - 1756.85 - 383.10 54 y 6 3826.70 350.00 18 di 3 - 1516.85 - 383.10 55 y 7 3793.70 350.00 19 di 4 - 1264.65 - 383.10 56 y 8 3760.70 350.00 20 di 5 - 1024.65 - 383.10 57 y 9 3727.70 350.00 21 dummy - 674.40 - 344.40 58 y 10 3694.70 3 50.00 22 dummy - 358.68 - 347.68 59 y 11 3661.70 350.00 23 dummy 179.53 - 337.73 60 y 12 3628.70 350.00 24 dummy 514.13 - 337.73 61 y 13 3595.70 350.00 25 di 6 1098.65 - 383.10 62 y 14 3562.70 350.00 26 di 7 1338.65 - 383.10 63 y 15 3529.70 350 .00 27 xck 1590.85 - 383.10 64 y 16 3496.70 350.00 28 /dispoff 1830.85 - 383.10 65 y 17 3463.70 350.00 29 dummy 2098.15 - 383.10 66 y 18 3430.70 350.00 30 lp 2534.85 - 383.10 67 y 19 3397.70 350.00 31 eio 1 2783.05 - 383.10 68 y 20 3364.70 35 0.00 32 fr 3040.25 - 383.10 69 y 21 3331.70 350.00 33 l/r 3280.25 - 383.10 70 y 22 3298.70 350.00 34 md 3532.45 - 383.10 71 y 23 3265.70 350.00 35 lgnd 3714.45 - 383.10 72 y 24 3232.70 350.00 36 gnd 3815.75 - 383.10 73 y 25 3199.70 350.00 37 gnd 3995.95 - 383.10 74 y 26 3166.70 350.00
ST8024S ver 0.39 page 23/27 2008/05/05 75 y 27 3133.70 350.00 124 y 76 1516.70 350.00 76 y 28 3100.70 350.00 125 y 77 1483.70 350.00 77 y 29 3067.70 350.00 126 y 78 1450.70 350.00 78 y 30 3034.70 350.00 127 y 79 1417.70 350.00 79 y 31 3001.70 350.00 128 y 80 1384.70 350.00 80 y 32 2968.70 350.00 129 y 81 1351.70 350.00 81 y 33 2935.70 350.00 130 y 82 1318.70 350.00 82 y 34 2902.70 350.00 131 y 83 1285.70 350.00 83 y 35 2869.70 350.00 132 y 84 1252.70 350.00 84 y 36 2836. 70 350.00 133 y 85 1219.70 350.00 85 y 37 2803.70 350.00 134 y 86 1186.70 350.00 86 y 38 2770.70 350.00 135 y 87 1153.70 350.00 87 y 39 2737.70 350.00 136 y 88 1120.70 350.00 88 y 40 2704.70 350.00 137 y 89 1087.70 350.00 89 y 41 2671.70 35 0.00 138 y 90 1054.70 350.00 90 y 42 2638.70 350.00 139 y 91 1021.70 350.00 91 y 43 2605.70 350.00 140 y 92 988.70 350.00 92 y 44 2572.70 350.00 141 y 93 955.70 350.00 93 y 45 2539.70 350.00 142 y 94 922.70 350.00 94 y 46 2506.70 350.00 143 y 95 889.70 350.00 95 y 47 2473.70 350.00 144 y 96 856.70 350.00 96 y 48 2440.70 350.00 145 y 97 823.70 350.00 97 y 49 2407.70 350.00 146 y 98 790.70 350.00 98 y 50 2374.70 350.00 147 y 99 757.70 350.00 99 y 51 2341.70 350.00 148 y 100 724.7 0 350.00 100 y 52 2308.70 350.00 149 y 101 691.70 350.00 101 y 53 2275.70 350.00 150 y 102 658.70 350.00 102 y 54 2242.70 350.00 151 y 103 625.70 350.00 103 y 55 2209.70 350.00 152 y 104 592.70 350.00 104 y 56 2176.70 350.00 153 y 105 559.70 350.00 105 y 57 2143.70 350.00 154 y 106 526.70 350.00 106 y 58 2110.70 350.00 155 y 107 493.70 350.00 107 y 59 2077.70 350.00 156 y 108 460.70 350.00 108 y 60 2044.70 350.00 157 y 109 427.70 350.00 109 y 61 2011.70 350.00 158 y 110 394.70 350.00 110 y 62 1978.70 350.00 159 y 111 361.70 350.00 111 y 63 1945.70 350.00 160 y 112 328.70 350.00 112 y 64 1912.70 350.00 161 y 113 295.70 350.00 113 y 65 1879.70 350.00 162 y 114 262.70 350.00 114 y 66 1846.70 350.00 163 y 115 229.70 350.00 115 y 67 1813.70 350.00 164 y 116 196.70 350.00 116 y 68 1780.70 350.00 165 y 117 163.70 350.00 117 y 69 1747.70 350.00 166 y 118 130.70 350.00 118 y 70 1714.70 350.00 167 y 119 97.70 350.00 119 y 71 1681.70 350.00 168 y 120 64.70 350 .00 120 y 72 1648.70 350.00 169 dummy 31.70 350.00 121 y 73 1615.70 350.00 170 dummy - 31.70 350.00 122 y 74 1582.70 350.00 171 y 121 - 64.70 350.00 123 y 75 1549.70 350.00 172 y 122 - 97.70 350.00 173 y 123 - 130.70 350.00 222 y 172 - 1747.70 350.00
ST8024S ver 0.39 page 24/27 2008/05/05 174 y 124 - 163.70 350.00 223 y 173 - 1780.70 350.00 175 y 125 - 196.70 350.00 224 y 174 - 1813.70 350.00 176 y 126 - 229.70 350.00 225 y 175 - 1846.70 350.00 177 y 127 - 262.70 350.00 226 y 176 - 1879.70 350.00 178 y 128 - 295.70 350.00 227 y 177 - 1912.70 350.00 179 y 129 - 328.70 350.00 228 y 178 - 1945.70 350.00 180 y 130 - 361.70 350.00 229 y 179 - 1978.70 350.00 181 y 131 - 394.70 350.00 230 y 180 - 2011.70 350.00 182 y 132 - 427.70 350.00 231 y 181 - 2044.70 350.00 183 y 133 - 460.70 350.00 232 y 182 - 2077.70 350.00 184 y 134 - 493.70 350.00 233 y 183 - 2110.70 350.00 185 y 135 - 526.70 350.00 234 y 184 - 2143.70 350.00 186 y 136 - 559.70 350.00 235 y 185 - 2176.70 350.00 187 y 137 - 592.70 350.00 236 y 186 - 2209.70 350.00 188 y 138 - 625.70 350.00 237 y 187 - 2242.70 350.00 189 y 139 - 658.70 350.00 238 y 188 - 2275.70 350.00 190 y 140 - 691.70 350.00 239 y 189 - 2308.70 350.00 191 y 141 - 724.70 350.00 240 y 190 - 2341.70 350.00 192 y 142 - 757.70 350.00 241 y 191 -2374.70 350.00 193 y 143 - 790.70 350.00 242 y 192 - 2407.70 350.00 194 y 144 - 823.70 350.00 243 y 193 - 2440.70 350.00 195 y 145 - 856.70 350.00 244 y 194 - 2473.70 350.00 196 y 146 - 889.70 350.00 245 y 195 - 2506.70 350.00 197 y 147 - 922.70 350.00 246 y 196 - 2539.70 350.00 198 y 148 - 955.70 350.00 247 y 197 - 2572.70 350.00 199 y 149 - 988.70 350.00 248 y 198 - 2605.70 350.00 200 y 150 - 1021.70 350.00 249 y 199 - 2638.70 350.00 201 y 151 - 1054.70 350.00 250 y 200 - 2671.70 350.00 202 y 152 -108 7.70 350.00 251 y 201 - 2704.70 350.00 203 y 153 - 1120.70 350.00 252 y 202 - 2737.70 350.00 204 y 154 - 1153.70 350.00 253 y 203 - 2770.70 350.00 205 y 155 - 1186.70 350.00 254 y 204 - 2803.70 350.00 206 y 156 - 1219.70 350.00 255 y 205 - 2836.70 350 .00 207 y 157 - 1252.70 350.00 256 y 206 - 2869.70 350.00 208 y 158 - 1285.70 350.00 257 y 207 - 2902.70 350.00 209 y 159 - 1318.70 350.00 258 y 208 - 2935.70 350.00 210 y 160 - 1351.70 350.00 259 y 209 - 2968.70 350.00 211 y 161 - 1384.70 350.00 260 y 210 - 3001.70 350.00 212 y 162 - 1417.70 350.00 261 y 211 - 3034.70 350.00 213 y 163 - 1450.70 350.00 262 y 212 - 3067.70 350.00 214 y 164 - 1483.70 350.00 263 y 213 - 3100.70 350.00 215 y 165 - 1516.70 350.00 264 y 214 - 3133.70 350.00 216 y 166 -1 549.70 350.00 265 y 215 - 3166.70 350.00 217 y 167 - 1582.70 350.00 266 y 216 - 3199.70 350.00 218 y 168 - 1615.70 350.00 267 y 217 - 3232.70 350.00 219 y 169 - 1648.70 350.00 268 y 218 - 3265.70 350.00 220 y 170 - 1681.70 350.00 269 y 219 - 3298.70 3 50.00 221 y 171 - 1714.70 350.00 270 y 220 - 3331.70 350.00 271 y 221 - 3364.70 350.00 284 y 234 - 3793.70 350.00 272 y 222 - 3397.70 350.00 285 y 235 - 3826.70 350.00
ST8024S ver 0.39 page 25/27 2008/05/05 273 y 223 - 3430.70 350.00 286 y 236 - 3859.70 350.00 274 y 224 - 3463.70 350.00 287 y 237 - 3892.70 350.00 275 y 225 - 3496.70 350.00 288 y 238 - 3925.70 350.00 276 y 226 - 3529.70 350.00 289 y 239 - 3958.70 350.00 277 y 227 - 3562.70 350.00 290 y 240 - 3991.70 350.00 278 y 228 - 3595.70 350.00 291 dummy - 4024.70 350.00 279 y 229 - 3628.70 350.00 292 dummy - 4057.70 350.00 280 y 230 - 3661.70 350.00 293 dummy - 4090.70 350.00 281 y 231 - 3694.70 350.00 294 dummy - 4123.70 350.00 282 y 232 - 3727.70 350.00 295 v 0l - 4192.50 350.00 283 y 233 - 3760.70 350.00 12.1 gold bump size pad no. x y area (um 2 ) 1, 43 112.00 18.00 2016.0000 2, 3, 4, 5, 39, 40, 41, 42 112.00 51.00 5712.0000 44, 295 87.00 122.00 10614.0000 6, 38 87.00 112.00 9744.0000 7, 37 99.00 42.40 4197.6000 8, 9, 35, 36 81.30 42.40 3447.1200 10 84.10 42.90 3620.7600 11 80.70 42.40 3421.6800 12, 13, 15~20, 25~28, 30~34 88.70 42.40 3760.8800 14, 29 100.20 42.40 4248.4800 21 43.30 44.40 1922.5200 22 52.85 37.85 2000.3725 23, 24 34.65 57.75 2001.0375 45~294 18.00 122.00 2196.0000 wafer thickness = 480 20um, bump pad height = 15um, strength=30g
ST8024S ver 0.39 page 26/27 2008/05/05 13. application note(reference only) 13.1 adjust v1 and v4 voltage to keep the v0-v1 = v4-vss relation to get better display quality. the (v0-v1)-(v4-vss) value had better less than 100mv. 13.2 add 0.1uf high frequency by-pass capacitor to filter the noise on v0~v4 to vss. 13.3 when op follower circuit is used, please be sure the op power is higher than v0 at least 1.5v. 13.4 eio1 and eio2 is enable pin for driver, please pay attention to the distance to avoid noise when cascade function is used. two chip connecting distance is as shorter as better.
ST8024S ver 0.39 page 27/27 2008/05/05 14. revision revision description page date 0.10 first release 1-25 2005/9/12 0.20 add lgnd definition, and re-define the pin function 1-25 2005/11/22 0.30 modify suggestion resistor value for v0. add alignment mark data, add lcd panel layout example modify bond pad height to 18um 21 2006/5/22 0.31 modify bump pad height to 15um and add wafer thickness. 24 2006/6/7 0.32 modify all vss for logic setting pins to lgnd 1-25 2006/7/21 0.33 modify description of lgnd 6-8 2006/7/21 0.34 change sitronix logo and modify description of lgnd for com mode 1-25 2006/7/21 0.35 modify pad define and size for pad no.6 and no.38. 21-24 2006/7/24 0.36 modify chip size and thickness with scribe line modify output resistance test condition 16,22,24 2006/10/26 0.37 modify v 0 max. voltage in recommended operating conditions and absolute maximum ratings modify the max. v 0 voltage to 40v for test condition modify v 0 max. voltage in feature 2,15-18 2007/1/3 0.38 modify all the data about absolute max voltage and recommend max voltage 2,16-18 2007/5/25 0.39 modify the ito resistor value suggestion add application note 21,26 2008/5/05 the above information is the exclusive intellectual property of sitronix technology corp. and shall not be disclosed, distributed or reproduced without permission from sitronix.

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